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CY2276A-21 CY2276A-31
Pentium(R)/II Clock Synthesizer/Driver for Desktop PCs with Intel 82440LX and 3-4 DIMMs
Features
* Mixed 2.5V and 3.3V operation * Single-chip clock solution to meet requirements of Pentium(R) and Pentium(R) II motherboards -- Multiple CPU clocks at 2.5V supporting single and dual-processor systems -- Seven synchronous PCI clocks -- Multiple 2.5V IOAPIC clocks at 14.318 MHz -- Multiple 3.3V SDRAM clocks -- Multiple 3.3V USB and I/O clocks -- Multiple 3.3V Ref. clocks at 14.318 MHz * I2CTM Serial Configuration Interface * Factory-EPROM programmable output drive and slew rate for EMI customization * Factory-EPROM programmable clock frequencies for custom configurations * High drive, low skew, and low jitter outputs * Available in space-saving 56-pin SSOP package outputs available from each device, as shown in the Selector Guide. The CY2276A-21 is ideal for four-SDRAM module or server applications that require sixteen SDRAM clocks, and do not require the ability to stop CPU clocks. The CY2276A-31 is ideal for single-processor or dual-processor desktop systems, which require an extra CPU clock. All CY2276A outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and factory-EPROM programmable output drive and slew-rate enable optimal configurations for EMI control.
CY2276A Selector Guide.
Clock Outputs CPU (60, 66.6 MHz) SDRAM PCI (CPU/2 MHz) IOAPIC (14.318 MHz) USB/IO (48 MHz) IO (24 MHz) Ref. (14.318 MHz) CPU-PCI delay -21 4 16 7 2 1 1 1 1-6 ns -31 5 13 7 2 2 0 2 1-5 ns
Functional Description
The CY2276A-21 andCY2276A-31 are single-chip clock generators for Pentium or Pentium II systems designed with the Intel(R) 82440LX or similar chipset. They differ in the number of
Logic Block Diagram
OE
IOAPIC (14.318 MHz) VDDQ2 XTALIN
XTALOUT
REF (14.318 MHz)
14.318 MHz OSC. CPU PLL
CPUCLK VDDCPU SDRAM
Available on -31 only
SEL
EPROM
/2 EPROM Prog. Delay
PCI [0-6]
SYS PLL /2
USBCLK (48 MHz) IOCLK (24 MHz)
SCLK SDATA
SERIAL INTERFACE CONTROL LOGIC
Please refer to Selector Guide for exact number of outputs on each device
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 October 12, 1998
CY2276A-21 CY2276A-31
Pin Configurations
56 SSOP Top View
AVDD IOCLK USBCLK VSS XTALIN XTALOUT REF0 VDDQ3 PCICLK6 PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 VSS SDRAM15 SDRAM14 VDDQ3 SDATA 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 IOAPIC0 IOAPIC1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VSS SDRAM12 SDRAM13 VSS OE MODE SCLK AVDD REF0 REF1 VSS XTALIN XTALOUT VDDQ3 PCICLK6 PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ3 PCICLK5 VSS USBCLK0 USBCLK1 VDDQ3 N/C SDRAM12 VSS SDRAM11 SDRAM10 VDDQ3 SDATA SCLK 1 2 3 4 5 6 7 8 9
56 SSOP Top View
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDQ2 IOAPIC0 IOAPIC1 VSS CPUCLK0 CPUCLK1 VDDCPU CPUCLK2 CPUCLK3 VSS CPUCLK4 SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VSS SDRAM8 SDRAM9 VSS SEL OE
CY2276A-21
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
2
CY2276A-31
10
10
CY2276A-21 CY2276A-31
Pin Summary
Name VDDQ3 VDDQ2 VDDCPU AVDD VSS XTALIN[1] XTALOUT
[1]
Pins (-21) 8, 16, 21, 27, 38, 44 56 50 1 4, 11, 18, 24, 32, 35, 41, 47, 53 5 6 46, 45, 43, 42, 40, 39, 37, 36, 23, 22, 20, 19, 34, 33, 26, 25 31 52, 51, 49, 48 10, 12, 13, 14, 15, 17, 9 55, 54 7 3 2 28 29 N/A 30 N/A N/A
Pins (-31) 7, 15, 20, 26, 37, 43 56 50 1 4, 10, 17, 23, 31, 34, 40, 47, 53 5 6 45, 44, 42, 41, 39, 38, 36, 35, 33, 32, 25, 24, 22 29 52, 51, 49, 48, 46 9, 11, 12, 13, 14, 16, 8 55, 54 2, 3 18, 19 N/A 27 28 N/A N/A 21 30
Description 3.3V Digital voltage supply IOAPIC Digital voltage supply, 2.5V CPU Digital voltage supply, 2.5V Analog voltage supply, 3.3V Ground
Reference crystal input Reference crystal feedback SDRAM clock outputs
SDRAM[0-15] (-21) SDRAM[0-12] (-31)
OE CPUCLK [0-3] (-21) CPUCLK [0-4] (-31) PCICLK [0-6] (All) IOAPIC [0-1] (All) REF0 (-21) REF [0-1] (-31) USBCLK (-21) USBCLK [0-1] (-31) IOCLK SDATA SCLK CPU_STOP MODE N/C SEL
Active HIGH output enable, disables all outputs when asserted CPU clock outputs PCI clock outputs, running at one-half the CPU frequency IOAPIC clock outputs Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load 48 MHz USB clock output 24 MHz I/O clock output Serial data input for serial configuration port Serial clock input for serial configuration port Active LOW input, disables CPU clocks when asserted Mode input, not used, tie to VSS Not connected. Tie to VSS CPU frequency select input (see Function Table)
Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
3
CY2276A-21 CY2276A-31
Function Table
Device -21 -21 -31 -31 -31 0 1 0 1 1 OE SEL N/A N/A X 0 1 XTALIN 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz CPUCLK SDRAM Hi-Z 66.67 MHz Hi-Z 60 MHz 66.67 MHz PCICLK Hi-Z 33.33 MHz Hi-Z 30 MHz 33.33 MHz REF IOAPIC Hi-Z 14.318 MHz Hi-Z 14.318 MHz 14.318 MHz Hi-Z 48 MHz Hi-Z 48 MHz 48 MHz USB I/O (-21 only) Hi-Z 24 MHz N/A N/A N/A
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK Target Frequency (MHz) 66.67 60.0 Actual Frequency (MHz) 66.654 60.0 0 PPM -195
CPU and PCI Clock Driver Strengths
* Matched impedances on both rising and falling edges on the output drivers * Output impedance: 25 (typical) measured at 1.5V.
Byte 0: Functional and Frequency Select Clock Register (1 = Enable, 0 = Disable)
Bit Pin # Description (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' (Reserved) drive to `0' Bit 1 1 1 0 0 Bit 0 1 - N/A 0 - N/A 1 - Testmode 0 - Normal Operation Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits should be programmed to "0". * I2C Address for the CY2276A-21,-31 is: A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W ----
Select Functions
Outputs Functional Description Test Mode CPU TCLK/2
[2]
PCI, PCI_F TCLK/4
SDRAM TCLK/2
Ref TCLK
IOAPIC TCLK
Note: 2. TCLK supplied on the XTALIN pin in Test Mode.
4
CY2276A-21 CY2276A-31
Byte 1: CPU Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description IOCLK (Active/Inactive) (-21 ONLY) USBCLK0 (Active/Inactive) (-31 ONLY) USBCLK (Active/Inactive) (-21 ONLY) USBCLK1 (Active/Inactive) (-31 ONLY) (Reserved) drive to `0' CPUCLK4 (Active/Inactive) (-31 ONLY) Not available on -21 CPUCLK3 (Active/Inactive) CPUCLK2 (Active/Inactive) CPUCLK1 (Active/Inactive) CPUCLK0 (Active/Inactive)
Byte 2: PCI Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved) drive to `0' PCICLK6 (Active/Inactive) PCICLK5 (Active/Inactive) PCICLK4 (Active/Inactive) PCICLK3 (Active/Inactive) PCICLK2 (Active/Inactive) PCICLK1 (Active/Inactive) PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description SDRAM15 (Active/Inactive) (-21 ONLY) Not available on -31 SDRAM14 (Active/Inactive) (-21 ONLY) Not available on -31 SDRAM13 (Active/Inactive) (-21 ONLY) Not available on -31 SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Description Bit 7 SDRAM7 (Active/Inactive) Bit 6 SDRAM6 (Active/Inactive) Bit 5 SDRAM5 (Active/Inactive) Bit 4 SDRAM4 (Active/Inactive) Bit 3 SDRAM3 (Active/Inactive) Bit 2 SDRAM2 (Active/Inactive) Bit 1 SDRAM1 (Active/Inactive) Bit 0 SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description (Reserved drive to `0') (Reserved) drive to `0' IOAPIC1 (Active/Inactive) IOAPIC0 (Active/Inactive) (Reserved) drive to `0' (Reserved) drive to `0' REF1 (Active/Inactive)(-31 ONLY) REF0 (Active/Inactive)
Byte 6: Reserved, for future use
5
CY2276A-21 CY2276A-31
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015, like VDD pins tied together)
Operating Conditions[3]
Parameter AVDD, V DDQ3 VDDCPU VDDQ2 TA CL CPU Supply Voltage IOAPIC Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on CPUCLK, USBCLK, IOCLK, REF[1:2], IOAPIC[0:1] PCICLK, SDRAM REF0 Reference Frequency, Oscillator Nominal Value Description Analog and Digital Supply Voltage Min. 3.135 2.375 2.375 0 10 30, 20 20 14.318 Max. 3.465 2.9 2.9 70 20 30 45 14.318 MHz Unit V V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL VILiic VOH VOL VOH Description High-level Input Voltage Low-level Input Voltage Low-level Input Voltage Except Crystal Inputs Except Crystal Inputs I2C inputs only IOH = 16 mA CPUCLK IOH = 18 mA IOAPIC Low-level Output Voltage[4] VDDCPU = 2.375V, VDDQ2 = 2.375V High-level Output Voltage
[4]
Test Conditions
Min. Max. Unit 2.0 0.8 0.7 2.0 0.4 2.4 V V V V V V
High-level Output Voltage[4] VDDCPU = 2.375V, VDDQ2 = 2.375V
IOL = 27 mA CPUCLK IOL = 29 mA IOAPIC IOH = 36 mA SDRAM IOH = 32 mA PCICLK IOH = 36 mA REF0
VDDQ3, AVDD, VDDCPU = 3.135V
VOL
Low-level Output Voltage
[4]
VDDQ3, AVDD, VDDCPU = 3.135V
IOL = 29 mA SDRAM IOL = 26 mA PCICLK IOL = 29 mA REF0
0.4V
V
IIH IIL IOZ IDD IDD
Input High Current Input Low Current Output Leakage Current Power Supply Current[4] Power Supply Current[4]
VIH = V DD VIL = 0V Three-state VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs, CPU clocks = 66.67 MHz VDD = 3.465V, V IN = 0 or VDD, Unloaded Outputs
-5 -10
+5 5 +10 310 130
A A A mA mA
Notes: 3. Electrical parameters are guaranteed with these operating conditions. 4. Parameter guaranteed by design and characterization. Not 100% tested in production.
6
CY2276A-21 CY2276A-31
CY2276A-21 Switching Characteristics[4,5] Over the Operating Range
Parameter t1 Output CPUCLK, SDRAM, REF0, IOAPIC PCI CPUCLK PCICLK CPUCLK PCICLK CPUCLK PCICLK SDRAM REF0 IOAPIC CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK PCICLK SDRAM CPUCLK, PCICLK, SDRAM Description Output Duty Cycle
[6]
Test Conditions t1 = t1A / t1B
Min. 45
Typ. 50
Max. 55
Unit %
t1 t1C t1C t1D t1D t2 t2 t2 t2 t2 t3 t4 t5 t6
Output Duty Cycle[6] CPU Clock HIGH Time PCI Clock HIGH Time CPU Clock LOW Time PCI Clock LOW Time CPU Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF0 Rising and Falling Edge Rate IOAPIC Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew
t1 = t1A / t1B Above 2.0V, 66.6 MHz, VDDCPU = 2.5V Above 2.4V, 33.3 MHz, VDD = 3.3V Below 0.4V, 66.6 MHz, VDDCPU = 2.5V Below 0.4V, 33.3 MHz, VDD = 3.3V Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 2.0V and 0.4V, VDDCPU = 2.5V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for CPU clocks and 1.5V for other clocks, VDDCPU = 2.5V, VDD = 3.3V Measured at 1.25V for CPU clocks and 1.5V for other clocks, VDDCPU = 2.5V, VDD = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDD = 3.3V CPU, PCI, and SDRAM clock stabilization from power-up
40 5.2 12.0 5.0 12.0 0.9 1.0 0.9 0.75 0.75 0.4 0.4
50
55
% ns ns ns ns
4.0 4.0 4.0 4.0 4.0 1.78 1.78 100 250 6.0 3.0
V/ns V/ns V/ns V/ns V/ns ns ns ps ns
1.0
t7
CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
650
ps
t8 t8 t9
400 500 3
ps ps ms
Notes: 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
7
CY2276A-21 CY2276A-31
CY2276A-31 Switching Characteristics[4,5] Over the Operating Range
Parameter t1 Output CPUCLK, SDRAM, REF0, IOAPIC PCI CPUCLK PCICLK CPUCLK PCICLK CPUCLK PCICLK SDRAM REF0 IOAPIC CPUCLK CPUCLK CPUCLK CPUCLK, PCICLK CPUCLK, SDRAM CPUCLK PCICLK SDRAM CPUCLK, PCICLK, SDRAM Description Output Duty Cycle
[6]
Test Conditions t1 = t1A / t1B
Min. 45
Typ. 50
Max. 55
Unit %
t1 t1C t1C t1D t1D t2 t2 t2 t2 t2 t3 t4 t5 t6
Output Duty Cycle[6] CPU Clock HIGH Time PCI Clock HIGH Time CPU Clock LOW Time PCI Clock LOW Time CPU Clock Rising and Falling Edge Rate PCI Clock Rising and Falling Edge Rate SDRAM Rising and Falling Edge Rate REF0 Rising and Falling Edge Rate IOAPIC Rising and Falling Edge Rate CPU Clock Rise Time CPU Clock Fall Time CPU-CPU Clock Skew CPU-PCI Clock Skew
t1 = t1A / t1B Above 2.0V, 66.6 MHz, VDDCPU = 2.5V Above 2.4V, 33.3 MHz, VDD = 3.3V Below 0.4V, 66.6 MHz, VDDCPU = 2.5V Below 0.4V, 33.3 MHz, VDD = 3.3V Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.0V Between 0.4V and 2.0V, VDDCPU = 2.5V Between 2.0V and 0.4V, VDDCPU = 2.5V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.25V for CPU clocks and 1.5V for other clocks, VDDCPU = 2.5V, VDD = 3.3V Measured at 1.25V for CPU clocks and 1.5V for other clocks, VDDCPU = 2.5V, VDD = 3.3V Measured at 1.25V, VDDCPU = 2.5V Measured at 1.5V, VDD = 3.3V CPU, PCI, and SDRAM clock stabilization from power-up
40 5.2 12.0 5.0 12.0 0.75 0.75 0.75 0.75 0.75 0.4 0.4
50
55
% ns ns ns ns
4.0 4.0 4.0 4.0 4.0 2.13 2.13 100 250 5.0 3.0
V/ns V/ns V/ns V/ns V/ns ns ns ps ns
1.0
t7
CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Power-up Time
650
ps
t8 t8 t9
500 550 3
ps ps ms
8
CY2276A-21 CY2276A-31
Timing Requirement for the I2C Bus
Parameter t10 t11 t12 t13 t14 t15 t16 SCLK Clock Frequency Time the bus must be free before a new transmission can start Hold time start condition. After this period the first clock pulse is generated. The Low period of the clock The High period of the clock Setup time for start condition. (Only relevant for a repeated start condition.) Hold time DATA for CBUS compatible masters for I2C devices DATA input set-up time Rise time of both SDATA and SCLK inputs Fall time of both SDATA and SCLK inputs Set-up time for stop condition 4.0 Description Min. 0 4.7 4 4.7 4 4.7 5 0 250 1 300 ns s ns s Max. 100 Unit kHz s s s s s s
t17 t18 t19 t20
Switching Waveforms
Duty Cycle Timing
t1A OUTPUT t1B
CPUCLK Outputs HIGH/LOW Time
t1C VDD OUTPUT 0V
t1D
All Outputs Rise/Fall Time
VDD OUTPUT t2 t3 t2 t4 0V
CPU-CPU Clock Skew
CPUCLK
CPUCLK t5
9
CY2276A-21 CY2276A-31
Switching Waveforms (continued)
CPU-SDRAM Clock Skew
CPUCLK
SDRAM t7
CPU-PCI Clock Skew
CPUCLK
PCICLK t6
Timing Requirements for the I2C Bus
SDA
t11 t18 t19
t12
SCL
t12 t13 t16 t14 t17 t15 t20
10
CY2276A-21 CY2276A-31
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
VDD2.5V/3.3V XTALIN XTALOUT Cx Cx VDDCPU Cd 0.1uF SCLOCK SDATA 60/66 SEL MODE VDD3.3V VDDQ3 AVDD Rs IOAPIC REF CPUCLK PCICLK USBCLK IOCLK SDRAM IOAPIC REF CPUCLK PCICLK USBCLK IOCLK (-31 only) SDRAM
SCLOCK SDATA 60/66 SEL MODE
Cd 0.1F VDD2.5V Cd 0.1F
VDDQ2
Ct VSS CY2276A-21,-31 56 PIN SSOP Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Cx = OPTIONAL LOAD MATCHING CAPACITOR Rs = SERIES TERMINATING RESISTORS
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, R out is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
11
CY2276A-21 CY2276A-31
Test Circuit
VDDQ3 VDDQ3
1 0.1 F 4
VDDQ2 56 0.1 F 53 0.1 F
1 4
VDDQ2 56 0.1 F 53
8 0.1 F 11 47 CY2276A-21 16 0.1 F 50 0.1 F
VDDCPU 0.1 F
7 50 10 47 15 CY2276A-31 0.1 F
VDDCPU
44
0.1 F
0.1 F
43
0.1 F
18
41 38 0.1 F 35 0.1 F
17
40 37 0.1 F 34
0.1 F
21
20
24
23
0.1 F
27
32 OUTPUTS CLOAD
0.1 F
26
31 OUTPUTS CLOAD
Note: All Capacitors must be placed as close to the pins as is physically possible
Ordering Information
Ordering Code CY2276APVC-21 CY2276APVC-31 Document #: 38-00611-D Package Name O56 O56 Package Type 56-Pin SSOP 56-Pin SSOP Operating Range Commercial Commercial
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CY2276A-21 CY2276A-31
Package Diagram
56-Lead Shrunk Small Outline Package O56
51-85062-B
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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